This invention relates generally to semiconductor devices and fabrication processes, and more particularly the invention relates to self-aligned MOSFET structures especially useful for ultra large scale integration (ULSI).
MOSFET technology is the dominant technology for VLSI (very large integrated circuits), whose applications can be found in microprocessors, application specific integrated circuits (ASIC), and semiconductor memories, currently a seventy billion dollar market with high growth potential. The device structures and the operation principles of MOSFET devices can be found in the book Physics of Semiconductor Devices by S. M. Sze, for example. One of the most important attractive features of MOSFET technology is that MOSFET devices can be built in a very small area, which facilitates very dense circuits and a high level of integration. Scaling is a term used to describe the continuous effort of building smaller MOSFET devices. The degree of scaling is commonly measured by the MOSFET channel length, which is defined by photolithography. Short channel (i.e., sub-micron) MOSFETs exhibit problems usually described as the short channel effect, which includes V.sub.T roll-off where the threshold voltage decreases as the channel length decreases; the drain-induced barrier lowering effect, DIBL, where the subthreshold current and the subthreshold swing increases with drain voltage; and the punchthrough effect where drain voltage causes current to flow deep under the channel. These effects emerge when the channel length is very short because the gate electrode loses control over the potential barrier in the channel between the source and the drain.
It is well known that for the gate to have stronger control over the potential barrier in the channel, the gate oxide thickness must decrease, and the substrate doping concentration must increase. Hence the common scaling scenario is to decrease the channel length, decrease the gate oxide thickness, and increase the substrate doping concentration. In principle, the substrate doping concentration can be increased in accordance with the thinness of the gate oxide to achieve the desirable threshold voltage and to suppress the short channel effect. This is usually achieved by a channel implant and a punchthrough-stopper implant. However, when the substrate doping concentration is too high, the carrier transport suffers from impurity scattering. Further, the junction capacitance that increases with higher substrate doping concentration adversely affects the MOSFET switching speed. Thus, to simply increase the substrate doping concentration straightforwardly in short channel MOSFET is the standard, but not an ideal, solution.
It is highly desirable to have a local, retrograded doping in the channel region. Local doping in the channel can keep the source and drain region from overlapping in a lightly-doped substrate thereby keeping junction capacitance small. Retrograded doping can ensure a robust punchthrough-stopper without using high impurity concentration in the channel thereby preventing mobility degradation. One proposal has been to use one additional photolithography step to shield the source/drain regions while performing the local doping implantation. However, this proposal is not desirable due to the additional photolithography step needed, which increases manufacturing cost. It should be noted that the added photolithography step is critical because it is in the gate region yet it is not self-aligned. Further, the implant has to be performed before the gate formation and thus will go through subsequent oxidation and thermal annealing steps such as gate oxidation and the source/drain annealing. Consequently, a high degree of vertical and lateral localization of the dopant atoms cannot be achieved, hence a high dopant dose is needed which results in mobility degradation and increased junction capacitance. Though this solution is not practical, it does demonstrate that if the junction capacitance is reduced, the gate delay time can reduced 40% from what is achievable with conventional MOSFET technology.
The present invention provides high speed MOSFET technology with relatively easy control of dopant diffusion and requires no additional or critical photolithography steps for the channel and the punchthrough stopper implant.